Senior ASIC Verification Engineer — SystemVerilog/UVM Expert
Listed on 2026-10-26
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Engineering
Test Engineer, Hardware Engineer, Quality Engineering
Empiric is seeking 5+ ASIC Verification Engineers for a global semiconductor manufacturing project. You will drive verification strategy, build advanced UVM/System Verilog test benches, and own verification plans for SoC/IP blocks.
The role is based in Bristol or Cambridge with a 12-month rolling contract and a start in December. You should bring strong UVM/System Verilog expertise, experience with constrained-random stimulus, coverage-driven verification, and good collaboration with RTL teams to
Step into the Senior ASIC Verification Engineer — System Verilog/UVM Expert role at Empiric in Cambridge, England, United Kingdom and grow with us.
We invite applications for the Senior ASIC Verification Engineer — System Verilog/UVM Expert position located in Cambridge, England, United Kingdom.
The following role is for a Senior ASIC Verification Engineer — System Verilog/UVM Expert with Empiric.
Our team is growing, and we are hiring a Senior ASIC Verification Engineer — System Verilog/UVM Expert in Cambridge, England, United Kingdom.
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