Electrical Engineering - Cleared Contractor - L5

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Job Description ... Security Clearance Level Required
- Secret (Refresh of JP7960) Lead/Senior FPGA Engineer
- Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. L3

Harris has state-of-the-art EDA flows/methodologies including Mentor EDA:
Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Client/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

• Derive FPGA design specifications from system requirements
• Develop detailed FPGA architecture for implementation
• Implement design in RTL (VHDL) and perform module level simulations
• Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
• Perform RTL quality using:
  Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), Static Formal EDA
• Generate verification test plans and perform End to End Simulations
• Support Board, FPGA bring up
• Validate design through HW/SW integration test with test equipment
• Support product collateral for NSA certification

• Bachelor of Science (BS)
  -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
• 5-7+ years experience designing FPGA products with VHDL
• Experience with Xilinx FPGAs and Vivado
• Experience with Revision control system
• Experience with Earned Value Management (EVM)
• Good written, verbal, and presentation skills
• Active DoD Security Clearance Preferred

• Experience with mapping algorithms to architecture
• Experience in C++ (OOP)
• Experience with any of protocols:
  Ethernet, TCP/IP, PCIe, NVMe, USB
• Experience with Xilinx SoC design with SDKs and Peta Linux OS
• Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

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