ASIC Digital Design Tech Lead

The application window is expected to close on: 01/18/2027

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development- from design to qualification to production is within the team, we're able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

As a Digital Design Technical Leader for Silicon One Optics, you won't just be building chips—you will architect the backbone of next-generation optical interconnects. From initial concept to tapeout and post-silicon production, you will own the full ASIC lifecycle and lead cross-functional engineering teams across digital, analog, firmware, and physical design. In this high-stakes role, you will define digital architectures, spearhead the integration of cutting-edge high-speed IPs (ODSP, D2D IP, Ser Des XSR/PAM4), and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics.

This is your opportunity to drive technical strategy, pioneer breakthrough interconnect innovations, and deliver silicon that powers the future of high-performance computing.

Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up (FPGA prototyping, lab validation, and ATE) for complex digital blocks and CPU subsystems.

Translate top-level requirements into high-speed datapath and low-speed control plane block specifications- balancing power, timing, loop dynamics, and hardware/firmware trade-offs.

Independently simulate and debug complex design issues, sign off on verification coverage, and support the integration of Ser Des and DSP IPs.

Support synthesis, DFT, low-power design, and timing closure while developing automation scripts to process Quality of Results (QoR) metrics.

Partner seamlessly with cross-functional teams to resolve technical design challenges and maintain system stability.

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation, Prior experience in managing the complete ASIC/SoC design flow Prior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed Ser Des, Ethernet, and D2D PHY IP.

End-to-End Silicon Lifecycle & Architecture:
Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up. Specification & Microarchitecture Design:
Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware vs. firmware trade-offs. Verification, Simulation & IP Integration:
Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating Ser Des and DSP IP. Implementation, Backend & Automation:
Hands-on experience with backend implementation…