Physical Design Technical Leader

The application window is expected to close on: 11/30/2026

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

Don't just watch the AI revolution happen—build the physical backbone powering it. As a Physical Design Engineer at Silicon One Optics, you will floorplan, tape out, and physically realize our next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs. You'll directly shape the silicon photonics that power hyper-scale AI/ML data centers worldwide. If you want your silicon in the most demanding networks on the planet, this is where you need to be.

• Full-Flow Ownership & First-Pass Tapeout:
  Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes, driving hierarchical floor planning, complex mixed-signal macro placement, and signoff (STA, IR/EM, PV) to ensure first-pass silicon success.

• Methodology & Flow Innovation:
  Architect and scale digital implementation flows, leveraging custom TCL/Python automation and close EDA vendor partnerships to elevate QoR, optimize turnaround time, and improve team-wide productivity.

• Cross-Functional Design Convergence:
  Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations, collaborating closely with RTL, Analog, DFT, Packaging, and CAD teams to resolve complex cross-domain bottlenecks.

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

• Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes

• Prior hands-on experience with the full physical design flow at block and/or chip level

• Prior hands-on expertise in EDA tool flows, back-end sign-off criteria, and workflow automation utilizing Python, TCL, and Shell scripts to maximize turnaround time and execution efficiency.

• Prior experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks

• Prior experience in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation for final sign-off timing closure.

• Prior experience in physical design fundamentals with proven ability to identify, debug, and fix complex Electromigration (EM), IR drop, RC parasitic extraction, and crosstalk/glitch violations.

• Prior hands‑on experience with functional equivalence checking and functional ECOs

• Prior experience in power grid design and optimization

• Good understanding of the Standard-Cell IP, memory compiler IP Selection Criteria

• Prior experience in integrating mixed-signal designs

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities…