Principal Memory Architect SoC IP

Max Linear is seeking a senior memory IP engineer to design and optimize memory architectures for SoC integration. You will lead SRAM and register-file based solutions, leveraging memory compilers or custom designs to achieve high performance, low power, and area efficiency.

You will guide roadmaps, participate in architecture selection, and drive PPA trade-offs with multi-disciplinary teams and external IP vendors.

This role, Principal Memory Architect:
High-Performance SoC IP at Max Linear, could be your next opportunity.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Principal Memory Architect:
High-Performance SoC IP role in the description above.

We appreciate your interest in this position.

Join Max Linear and contribute to our ongoing work.

Take a moment to read everything above and see whether this role is right for you.