Principal Engineer Memory Architect

• Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes
• Leverage your memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration
• Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness
• Own the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs
• Deliver competitive memory IP solutions and enabling seamless integration into So Cs
• Collaborate with cross-functional engineering teams and external IP vendors, and developing scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation

• Deep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs
• Strong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining and power integrity considerations
• Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs
• Strong understanding of memory compiler flows and verification methodologies, with the ability to assess both compiled and custom memory solutions
• Excellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at both strategic and hands‑on levels
• Preferred Qualifications
  • Proficiency with EDA and analysis tools HSPICE, Spectre, Python, and related memory verification or modeling environments
  • Familiarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols
  • Familiarity with ROMs, flash memories, OTPs is a plus
  • Understanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices
  • Familiarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso, is a plus
  • Experience with QA methodologies, validation frameworks, technical roadmaps
• BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience

Max Linear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation.

Max Linear's good faith estimate starting base salary range is: $135,000 to $ 198,000 Annually

We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.

The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.

Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.

Max Linear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless…