Principal Product Engineer- Physical Layer

Principal Product Engineer - Physical Layer

Industrial:
Semiconductor Manufacturing, Computer and Network Security, and Appliances, Electrical, and Electronics Manufacturing

Position Overview

The Principal Product Engineer is a critical technical interface between Cadence and top-tier customers, ensuring high-quality support and engagement throughout the lifecycle of customer programs. The engineer is responsible for managing all technical communications, driving resolution of customer issues, coordinating critical technical reviews, and ensuring successful silicon bring-up and product integration. The engineer also collaborates closely with internal design, validation, and applications teams as well as the customer’s program manager to deliver high-quality outcomes on aggressive schedules.

Key Responsibilities

• Primary Technical Liaison: Act as the main technical point of contact for customer engineering teams; attend and lead weekly customer calls organized by program management.
• Program Integration: Ensure inclusion in all relevant customer communications, technical deep-dives, and milestone reviews; provide status updates and action tracking.
• Protocol & Physical Layer: Demonstrate a strong understanding of Physical and Protocol layers for at least one high-speed interface (e.g., PCIe, Ethernet, USB, CXL, UCIe).
• State Machines & Standards: Familiarity with PCIe/UCIe LTSSM states and major Ethernet standards; interpret specs, debug link training, and compliance behaviors.
• Lab Equipment Proficiency: Hands‑on experience with oscilloscopes, BERTs, protocol exercisers, and analyzers.
• Debugging & Analysis: Diagnose silicon-related issues and interpret test results effectively.
• Technical Issue Management: Own all support cases filed by the customer across platforms such as SFDC, Sherlock, and Jira.
• Prioritization: Evaluate and triage incoming cases, determine severity and urgency, and ensure timely resolution in alignment with agreed service levels.
• Escalation Point: Serve as the technical escalation path for complex issues requiring cross‑functional involvement (design, validation, firmware, applications).
• Technical Review Coordination: Organize and lead reviews such as SDC/constraint checks, physical integration assessments, pre‑tape‑out checklist reviews, and bring‑up test plan evaluations.
• Customer Engagement: Collaborate closely with the customer program manager to ensure smooth communication and inclusion in all relevant meetings.
• Documentation & Reporting: Maintain standardized documentation including kickoff materials, status dashboards, and silicon reports; track case metrics and provide progress updates.
• AI Incorporation: Leverage AI‑powered tools and assistants to enhance productivity, improve decision making, and maintain high‑quality customer deliverables; apply AI‑powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.

Required Skills & Qualifications

• Bachelor’s in computer science or electrical engineering with +7 years of relevant experience, or Master’s with +5 years of related experience.
• Skilled at listening to customer concerns and identifying potential issues early.
• Strong commitment to customer satisfaction and timely case resolution.
• Broad technical background in relevant IPs (both hard and soft) and product engineering.
• Strong communication and organizational abilities.
• Experience performing Physical Layer and Protocol Layer validation for at least one high-speed SERDES technology.
• Hands‑on experience with post‑silicon PHY bring‑up, system interoperability, and compliance testing activities.
• Proficiency in using protocol analyzers, BERTs, and oscilloscopes.
• Familiarity with case management systems such as SFDC and Jira.
• Ability to prioritize cases, anticipate escalations, and manage technical reviews effectively.
• High-level understanding of technical issues with the capability to coordinate with subject matter experts.
• Proactive in gathering feedback and driving continuous improvement initiatives.
• Able to travel onsite to support customers with silicon bring‑up and debug (10% travel).

We’re doing work that matters. Help us solve what others can’t.

Mid‑Senior level

Full‑time

Engineering and Research

• Medical insurance
• Vision insurance
• 401(k)
• Paid maternity leave
• Paid paternity leave
• Tuition assistance

Base pay range: $117,600 – $218,400 per year