Lead Design Engineer — RTL, Timing & Tapeout
Listed on 2026-10-06
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Engineering
Electronics Engineer, Hardware Engineer, Engineering Design & Technologists, Test Engineer
Cadence Design Systems in Cary, NC seeks an experienced IC design engineer to lead timing closure and tape-out activities for Palladium and Protium SOCs. You will contribute to RTL synthesis, floor planning, clock-tree construction, and physical verification, collaborating with Front End RTL and Back End Verification teams.
The role requires 5+ years of E/E experience or 3+ years with MS, proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus), and familiarity with 5nm/3nm/2nm
We have an opening for a Lead Design Engineer — RTL, Timing & Tapeout in Cary, NC, United States within Engineering.
The position is based in Cary, NC, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 120..
We aim to respond to suitable candidates as soon as possible.
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