Senior Design Engineer: SOCs, RTL & Timing Expert
Listed on 2026-10-15
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Engineering
Electronics Engineer, Systems Engineer, Hardware Engineer, Engineering Design & Technologists
Cadence in the United States is seeking an experienced hardware senior engineer to lead a team that designs SOCs and sub-system chips. You will oversee RTL synthesis, floor planning, clock trees, timing closure, IR drop, and physical verification, coordinating Front End RTL and Back End verification teams.
Required BS in Electrical Engineering with 7+ years (MS 5+ years or PhD 1+ year). Proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and exposure to 5nm/3nm/2nm nodes,
Consider building your career as a Senior Design Engineer: SOCs, RTL & Timing Expert at Cadence.
The Senior Design Engineer: SOCs, RTL & Timing Expert role at Cadence is now open for applications in Cary, NC, United States.
Join us at Cadence as our next Senior Design Engineer: SOCs, RTL & Timing Expert in Cary, NC, United States.
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