DFT Engineer – SoC Test & Debug

Cadence Design Systems seeks an experienced DFT engineer to define and implement SoC-level DFT across large designs. You will develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG while driving pre-silicon sign-off and post-silicon debugging.

Collaboration with RTL, verification, physical design and operations teams is essential to success. The role emphasizes hands-on DFT, strong problem solving, and the ability to operate within a cross-functional engineering environment.

Our organisation is growing, and we are hiring a DFT Engineer I – SoC Test & Debug in Cary, NC, United States.

We are seeking a motivated DFT Engineer I – SoC Test & Debug to join Cadence Design Systems in Cary, NC, United States.

Consider building your career as a DFT Engineer I – SoC Test & Debug at Cadence Design Systems.