Principal Electrical Engineer ASIC/FPGA; Onsite
Job in
Cedar Rapids, Linn County, Iowa, 52402, USA
Listed on 2026-10-15
Listing for:
Raytheon
Full Time
position Listed on 2026-10-15
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Test Engineer, Aerospace / Aviation / Avionics
Job Description & How to Apply Below
Job d:
Posted Today
Start Date:
Location:
US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108
Country:
United States of America Time Type:
Full time
Date Posted:
Country:
United States of America
Location:
US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108
Position Role Type:
Onsite
U.S. Citizen, U.S. Person, or Immigration Status Requirements:
The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
Security Clearance Type:
DoD Clearance:
Secret
Security Clearance Status:
Active and existing security clearance required after day 1
Joining Collins Aerospace isn’t just about finding a job; it’s about embarking on a journey to redefine the future of aerospace technology.
Collins Aerospace, an RTX company, is a leader in technologically advanced and intelligent solutions for the global aerospace and defense industry. Collins Aerospace has the capabilities, comprehensive portfolio, and expertise to solve customers’ toughest challenges and to meet the demands of a rapidly evolving global market. This position is for a motivated Principal Electrical or Computer engineering candidate to be involved in the design, implementation, verification, and integration of a wide variety of high-performance digital ASICs and FPGAs applied to signal processing and information assurance products across Mission Systems on the Microelectronics Technology team.
What You Will Do:
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow Contribute to engineering estimates for new program pursuits
Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status Qualifications You Must Have:
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience oran Advanced Degree in a related field and minimum 5 years of experience
The ability to obtain and maintain a U.S. government issued secret security clearance is required.
U.S. citizenship is required, as only U.S. citizens are eligible for a security clearanceRTL coding and simulation in VHDL or Verilog Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure Testbench development for the verification of RTL blocks using VHDL or System Verilog. Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools) Familiarity with revision control concepts and tools (e.g. Git, Subversion) Qualifications We Prefer:
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, System Verilog) ASIC / FPGA lab validation with advanced lab equipment Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones.
Strong oral and written communication skills with the ability to document and present one's work and status Design for Test (DFT) and manufacturability issues
Experience with Unix, scripting, C/C++, and/or Perl Do you want to be a part of something bigger? A team whose impact stretches across the world, and even beyond? At Collins Aerospace, our Mission Systems team helps civilian, military and government customers complete their most complex missions — whatever and wherever they may be. Our customers depend on us for intelligent and secure communications, miss ionized…
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