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Senior DV Engineer: UVM Testbenches SoC IPs; Equity
Job in
City of Westminster, Central London, Greater London, England, UK
Listed on 2026-09-08
Listing for:
Baya Systems
Full Time
position Listed on 2026-09-08
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Location: City of Westminster
Baya Systems is seeking a seasoned Design Verification engineer to design and implement test benches for complex IPs, chips and interconnects. You will create test plans and write UVM/System Verilog code to verify multi-chiplet interconnects and No
Cs.
You will collaborate with software and design teams, debug failures, drive coverage, and contribute to the technology portfolio. Requirements include 8+ years in verification, Verilog/System Verilog, UVM, Python, and AMBA/CHI protocol knowledge.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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