Senior FPGA Engineer III

Overview

Senior FPGA Engineer III role at Comtech Telecommunications Corp. Chandler, AZ – Onsite 5 Days a Week.

Senior FPGA Designer with experience in the entire design flow for complex FPGA’s.

• Design, develop, document, debug and test FPGA SoC systems; including IP Integration into FPGA Projects (synthesis/implementation)
• High-Performance FPGA IP (VHDL/System Verilog)
• Userspace Drivers for FPGA IP (C++)
• Firmware for Embedded Microcontrollers (C)
• Utilize strong communication skills to effectively work and communicate with team members and engineering management.

• Strong digital design engineer with FPGA/ASIC SoC design experience
• Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
• Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
• Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
• Capable of creating RTL simulations to identify and resolve most issues before hardware tests
• Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
• Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
• Experience contributing to schematic capture and layout for FPGA portions of PCB designs
• Experience implementing at least one Gigabit Transceiver Protocol: PCI Express, Interlaken, USB Super Speed
• 1000
  
  BASE-X/SGMII, 10
  
  GBASE-R, 40
  
  GBASE-4, 100
  
  GBASE-R4
• Experience implementing Network Protocols, such as: L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G); L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP; L4: VITA 49.2, IEEE-ISTO 4900 DIFI and/or eCPRi (Highly Desired)
• Proficient in SW development with C, C++ and GIT version control
• Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
• Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams

• Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
• Working knowledge of Embedded Linux:
  Kernel / Yocto / U-Boot / Device Tree
• Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3
  
  GPP Rel 17/18
• Working knowledge of communication networks and security within a zero-trust environment
• Experience with Partial Reconfiguration/DFX or PCIe CvP
• Possess an active DoD clearance or demonstrate readiness to obtain one

• Bachelors in Electrical or Computer Engineering (or related degree).

• 5+ years of FPGA/ASIC SoC design experience.

Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.