Senior Verification Architect - SystemVerilog/UVM
Listed on 2026-10-13
-
Engineering
Test Engineer
Renesas Electronics is seeking a Principal Design Verification Engineer in Chandler, AZ to provide technical leadership for verification of next-generation memory interface products. This role will drive verification strategy and execution for complex digital designs, working closely with design teams to ensure functionality, performance, and product requirements are met.
The ideal candidate brings deep semiconductor verification expertise with System Verilog and UVM.
This role, Senior Verification Architect
- System Verilog/UVM at Renesas, could be your next move.
The position is based in Chandler, AZ, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 150..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Verification Architect
- System Verilog/UVM role in the description above.
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