FPGA Design Engineer – Early‑Career; Secret Clearance
Listed on 2026-10-13
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Engineering
Electronics Engineer, Test Engineer, Aerospace / Aviation / Avionics, Systems Engineer
Northrop Grumman Space Systems in Chandler, AZ is seeking an FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will collaborate with FPGA and cross-disciplinary teams to design, verify, and integrate FPGAs for advanced systems, under guidance in an early-career role.
This position requires a Bachelor’s in EE/CE with 2+ years experience or a Master’s degree, DoD Secret clearance eligibility, and experience with HDL (VHDL/Verilog), Vivado, and FPGA tooling.
We are seeking a motivated FPGA Design Engineer – Early‑Career (Secret Clearance) to join Northrop Grumman in Chandler, AZ, United States.
The advertised compensation is 87..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the FPGA Design Engineer – Early‑Career (Secret Clearance) role in the description above.
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