Semiconductor Packaging Integration Research Manager

About the Team

Foundry Technology Research is responsible for developing the breakthrough technologies that will power future generations of semiconductor manufacturing. The team conducts advanced research in devices, materials, interconnects, patterning, packaging, heterogeneous integration, and system technologies, while partnering closely with technology development, manufacturing, and external research ecosystems. Researchers help translate pioneering concepts into viable semiconductor solutions that influence Intel Foundry's long‑term roadmap and future customer offerings.

The Semiconductor Packaging Integration Research Manager is responsible for leading advanced packaging integration research to enable next‑generation heterogeneous semiconductor technology and systems. This role defines and drives early‑stage integration strategies across package architecture, chiplet assembly, substrate/interposer technology, wafer‑level and die‑level integration reliability, and manufacturability. The manager guides exploratory concepts from research to pathfinding through feasibility demonstration, prototype learning, technology readiness assessment, and transfer to development or manufacturing teams, while partnering closely with device, design, process, materials, reliability, modeling, test, manufacturing, university, supplier, and foundry ecosystem partners.

• Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3
  
  DIC, hybrid bonding, wafer‑level packaging, and emerging die‑to‑die interconnect technologies.
• Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system‑level scaling requirements.
• Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads.
• Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
• Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross‑domain integration gaps.
• Drive feasibility studies, architecture trade‑off analysis, process module evaluation, design rule development, prototyping, design‑of‑experiments, and experimental validation for new integration concepts.
• Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early‑stage packaging options.
• Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer related to advanced packaging integration.
• Guide research‑to‑development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
• Communicate technical progress, trade‑offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.

• Si‑Package co‑optimization across process, integration, electrical, thermal, mechanical, reliability, manufacturability, and cost dimensions
• Advanced packaging integration research leadership and technical vision
• Heterogeneous integration, chiplet, 2.5D/3
  
  DIC, hybrid bonding, and emerging interconnect expertise
• Technology pathfinding, roadmap definition, research portfolio management, and research‑to‑development transfer
• Modeling, simulation, prototyping, experimentation, failure analysis, and…