Hybrid VLSI Verification Intern — SystemVerilog & UVM
Listed on 2026-10-11
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Engineering
Hewlett Packard Enterprise Company in Wisconsin is offering a VLSI Design Verification Internship. You will work with experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for Slingshot, learning System Verilog and UVM verification techniques.
The internship targets students pursuing a bachelor's or master's degree in EE/CE/CS, with experience in object-oriented programming, strong problem-solving, and good communication.
This opening is for the Hybrid VLSI Verification Intern — System Verilog & UVM role at Hewlett Packard Enterprise Company.
All applications are reviewed carefully by our team.
The position is based in Chippewa Falls, WI, United States.
This opportunity is part of our work in IT & Technology, Other.
The advertised compensation is 48.000 - 56.000.
We aim to respond to suitable candidates as soon as possible.
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