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Senior ASIC​/FPGA Design Engineer; Low Power

Job in Clearfield, Davis County, Utah, 84016, USA
Listing for: Draper
Full Time position
Listed on 2025-12-20
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 82300 - 205750 USD Yearly USD 82300.00 205750.00 YEAR
Job Description & How to Apply Below
Position: Senior ASIC/FPGA Design Engineer (Low Power)
A nonprofit research and development company is seeking a Senior ASIC Hardware Engineer to design and simulate circuits, contribute to system-level design, and optimize designs for various criteria. Ideal candidates will have 7-10 years of experience and a bachelor's degree in Engineering. Competitive salary range from $82,300 to $205,750, with opportunities for growth in a collaborative environment.
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Position Requirements
10+ Years work experience
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