Lead verification Engineer

ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start-ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges.

With a multi-cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge-building environment.

Key Responsibilities:

• Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.
• Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.
• Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe connected via NoC.
• Model and validate credit-based flow control, packet routing, QoS, and virtual channel behavior.
• Perform assertion-based verification (SVA/DVL) for protocol compliance and corner cases.
• Debug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations.
• Work closely with architects and RTL teams to align verification coverage and performance metrics.
• Perform coverage closure (code + functional) and ensure complete verification sign-off.

• Strong experience with System Verilog, UVM, and object-oriented testbench development.
• In-depth knowledge of NoC protocols (AXI4, CHI, Tile Link, or proprietary NoC).
• Verification experience with coherent interconnects, cacheable traffic, and memory subsystem validation.
• Familiarity with Synopsys, Cadence, or Siemens verification tools (VCS/Xcelium/Questa).
• Familiarity with formal verification, assertions (SVA/PSL), and coverage metrics.
• Ability to debug low-level issues using waveform analysis, scoreboards, and transactors.
• Familiarity with multi-core CPU, DSP, or GPU interconnect systems is a plus.

Please update / fill the details referred here in above