Quantum Design Enablement Engineer

Quantum Design Enablement Engineer at IonQ, College Park, Maryland, United States. A mid-level full time position in the Compute - Engineering team, listed under hardware engineering.

About IonQ:
IonQ, Inc . [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.

In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance . Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space.

IonQ is making quantum platforms more accessible and impactful than ever before. We are seeking a Quantum Design Enablement Engineer to join our Manufacturing team in our mission to build the world’s best quantum computers. In this role, you will serve as the primary technical interface between internal quantum chip designers and external foundry partners, playing a key role in bringing next-generation trapped-ion hardware to life.

You will ensure our quantum chip designs transition seamlessly into reliable, scalable fabrication. Core responsibilities include managing the tapeout flow, executing physical verification, performing hands-on layout for test structures and reticle assembly, and partnering with foundries to refine our Process Design Kit (PDK). Key Responsibilities Foundry Interface & PDK Management:
Serve as the primary technical point of contact with external foundry partners. Work collaboratively to define, implement, and tr

• Bachelor’s or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related technical field.
• 3 - 5 years of industry experience in semiconductor manufacturing, design enablement, tapeout operations, or a closely related field.
• Hands-on experience with physical verification tools (such as Siemens Calibre, Cadence Pegasus, or Synopsys IC Validator) and running standard DRC, LVS, and ERC checks.
• Proficiency with standard layout and viewing tools like Cadence Virtuoso or KLayout, including the ability to perform layout edits and detailed mask reviews.
• Strong understanding of PDK architecture and technology files, as well as how foundry design rules dictate layout methodologies.
• Exceptional cross-functional communication skills, with demonstrated ability to negotiate technical requirements between external fab engineers and internal design teams.
• Strong proficiency in Python and hands-on experience with Python-based layout generation frameworks (such as gdsfactory, gdspy or the KLayout), alongside version control using Git.
• Experience with non-traditional semiconductor and microfabrication technologies, such as integrated photonics, MEMS, or specialized BEOL metallization.

• Strong proficiency in Python and hands-on experience with Python-based layout generation frameworks (such as gdsfactory, gdspy or the KLayout), alongside version control using Git.
• Experience with non-traditional semiconductor and microfabrication technologies, such as integrated photonics, MEMS, or specialized BEOL metallization.
• Experience writing or modifying custom physical verification rules (such as Calibre SVRF/TVF or equivalent) to develop layout rules specific to trapped-ion quantum computing hardware.
• Familiarity with standard CMOS device modeling principles and compact modeling methodologies.
• Understanding of Parasitic Extraction (PEX) flows and tools, with an awareness of how physical layout impacts parasitic capacitances, RF performance, and device behavior.