RTL Design Engineer

Battelle delivers when others can’t. We conduct research and development, manage national laboratories, design and manufacture products and deliver critical services for our clients—whether they are a multi-national corporation, a small start-up or a government agency.

We recognize and appreciate the value and contributions of individuals from a wide range of backgrounds and experiences and welcome all qualified individuals to apply.

Job Summary Battelle's Advanced Microsystem Solution Business Line develops advanced integrated circuit technologies and hardware assurance solutions for government and commercial customers. We are seeking an RTL Design Engineer to support the design and implementation of advanced digital integrated circuits and systems-on-chip (SoCs) in our Columbus, Ohio location.

As a RTL (Register Transfer Level) Design Engineer, you will develop microarchitectures, implement RTL designs, and optimize digital systems for performance, power, and area. The ideal candidate will have experience with Verilog/System Verilog design, synthesis, timing analysis, low power methodologies, and modern SoC development flows.

This role offers the opportunity to contribute to cutting-edge microelectronics research and development programs. Successful candidates will work closely with verification, physical design, and system engineering teams to deliver high-quality digital designs for advanced computing and secure hardware applications.

Responsibilities Design and implement RTL code for digital logic blocks and subsystems

Develop microarchitecture specifications and design documents

Optimize designs for performance, power, and area (PPA)
Perform RTL synthesis and work towards timing closure

Collaborate with verification engineers to ensure design quality and coverage

Debug design issues identified during verification and silicon validation

Participate in design reviews and provide technical guidance

Create and maintain design documentation and specifications

Implement design for testability (DFT) structures

Work with physical design team on timing constraints and floor planning

Analyze and resolve CDC and lint violations

Key Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field3+ years of RTL design experience

Strong Verilog/System Verilog RTL design experience

Deep understanding of digital design fundamentals and computer architecture

Microarchitecture design and optimization experience

Knowledge of synthesis, timing analysis, and static timing analysis (STA)

Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens)
Understanding of low power design techniques and power optimization

Experience with clock domain crossing (CDC) designScripting skills (Python, TCL) for design automation

Knowledge of design for testability (DFT) concepts

Knowledge of Version Control (Git)
Must be a US Citizen and able to obtain and maintain a US Government security clearance

Preferred Qualifications FPGA design and prototyping experience

Experience in low power methodologies (UPF, power gating, voltage scaling)
Knowledge of bus protocols (AXI, AHB, APB, ACE)

Experience with SoC integration and subsystem design

Understanding of performance modeling and analysis

Experience with lint and CDC checking tools

Knowledge of security design principles

Experience with assured microelectronics and hardware security principles (cryptography, side-channel, fault injection, radiation tolerance, hardware CWEs, etc.)Active Secret or Top-Secret US Government security clearance

Compensation Data Battelle is committed to fair and equitable compensation practices. The salary range for this role is $86,400 – $123,100 per year, in addition to our comprehensive benefits package. A…