Integrated Circuit Design Verification Engineer Job Columbus area,Ohio USA,Engineering

Battelle delivers when others can’t. We conduct research and development, manage national laboratories, design and manufacture products and deliver critical services for our clients—whether they are a multi-national corporation, a small start-up or a government agency.

We recognize and appreciate the value and contributions of individuals from a wide range of backgrounds and experiences and welcome all qualified individuals to apply.

Job Summary

Battelle's Advanced Microsystem Solutions Division develops advanced integrated circuit technologies and hardware assurance solutions for government and commercial customers. We are seeking an RTL Verification Engineer to support the verification and validation of complex digital integrated circuits and systems-on-chip (SoCs) in our Columbus, Ohio location.

As an RTL Verification Engineer III, you will develop and execute verification strategies for advanced digital designs, working closely with design and architecture teams throughout the development lifecycle. The ideal candidate will have experience building Universal Verification Methodology (UVM) based verification environments, developing System Verilog test benches, and performing functional verification at both the block and SoC level.

This role offers the opportunity to contribute to cutting-edge microelectronics programs involving secure and high-performance computing technologies. Successful candidates will be technically curious, detail-oriented, and motivated to solve challenging verification problems in a collaborative engineering environment.

Responsibilities

Develop and maintain UVM-based verification environments for block and SoC level designs
Write SoC test benches and verification code
Create comprehensive verification plans and test strategies
Implement constrained random tests and directed tests
Develop functional coverage models and analyze coverage metrics
Debug RTL and testbench issues, perform root cause analysis
Collaborate with design engineers to review specifications and identify verification requirements
Review and enhance verification infrastructure and methodologies
Run regression testing and track verification progress
Document verification results and present status to team and/or project leadership

Key Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
Minimum of 3 years of digital design verification experience
Universal Verification Methodology (UVM) expertise
Strong System Verilog knowledge
System Verilog TLM (Transaction Level Modeling) development experience
Experience with C++ programming for DPI (Direct Programming Interface) integration with System Verilog models
Experience with C programming for bare metal embedded systems development
Block level and SoC level validation experience
Verification planning and test plan development experience
Functional coverage and code coverage analysis experience
Experience with constrained random verification techniques
Debug and root cause analysis skills
Understanding of digital design concepts and microarchitecture
Knowledge of Version Control (Git)
Must be a US Citizen and able to obtain and maintain US Government security clearance

Preferred Qualifications

Formal verification experience (model checking, property verification)
System Verilog Assertions (SVA) design and verification experience
Python Programming experience
Low power verification (UPF) experience
Hardware/software co-verification experience
Bus protocol knowledge (AXI, AHB, APB, PCIe, etc.)
Knowledge of RISC-V ISA
Familiarity with emulation and FPGA prototyping
Experience with verification IP (VIP) development
Experience with assured microelectronics and hardware security principles (cryptography, side-channel,…