Entry-Level FPGA Verification Engineer; SystemVerilog​/UVM

Banking Soft Solutions LLC is seeking an entry-level FPGA design verification engineer in San Jose, CA. The role focuses on testing FPGA designs using System Verilog and UVM test benches, with scripting in Perl or Python to automate tests.

You will work closely with hardware cryptography teams and FPGA platform engineers to validate features and ensure robust verification methodologies are applied.

We invite applications for the Entry-Level FPGA Verification Engineer (System Verilog/UVM) position located in Columbus, OH, United States.

This role is for the Entry-Level FPGA Verification Engineer (System Verilog/UVM) role at Banking Soft Solutions LLC.

We are seeking a motivated Entry-Level FPGA Verification Engineer (System Verilog/UVM) to join Banking Soft Solutions LLC in Columbus, OH, United States.

Consider building your career as a Entry-Level FPGA Verification Engineer (System Verilog/UVM) at Banking Soft Solutions LLC.