Hardware Security Technical Leader - Hyperscaler Hybrid

The application window is expected to close on: 11/29/2026. This role is hybrid in Raleigh, North Carolina (RTP). 3 days onsite per week.

The Security & Trust Organization (S&TO) has corporate-level responsibility for customer data protection and compliance, corporate information protection, and government and product security. Security is a key concern of our customers and a top investment area for Cisco. Join us and help us become the #1 Trusted IT Company in the World! Within S&TO, the Foundational Security Technologies (FST) team seeks to increase product security and trustworthiness across a broad range of Cisco products through development, integration and deployment of reusable software and hardware solutions.

Within Foundational Security, the Hardware & Firmware Security Team (HFST) focuses on security solutions implemented at the hardware and firmware level.

Focus on Hyperscaler Security, play a pivotal role in ensuring Cisco's next-generation platforms and custom Hyperscaler hardware architectures adhere to meticulous security, trust, and resilience standards. Own the analysis of sophisticated systems from the high-level architecture down to component-level silicon, guiding multi-functional engineering teams and external partners to deliver robust, secure hardware solutions. Background in hardware design, low-level architecture, and security principles.

Enjoy translating sophisticated technical standards into practical engineering requirements and partnering across disciplinary boundaries to tackle challenging hardware security problems. Communicate technical concepts clearly through engineering documentation and multi-functional teamwork, and thrive when driving multiple parallel technical initiatives in a dynamic environment!

• Provide clear, actionable security requirements and architectural design guidance to product teams, hardware design engineers, firmware/BIOS teams, and third-party vendors.
• Provide technical mentorship to members of the Security and Trust engineering team.
• Coordinate and represent Cisco's technical interests in key external open-source and standards groups, such as the Open Compute Project (OCP) and Software for Open Networking in the Cloud (SONiC) Security Working Groups.
• Evaluate system-level hardware designs, schematics, board architectures, and component datasheets to identify threat vectors, vulnerabilities, and compliance gaps.
• Interpret, apply, and establish requirements aligned with emerging industry standards and compliance frameworks, including NIST SP 800-193 (Platform Firmware Resiliency), NSA CNSA 2.0 (Post-Quantum Cryptography / CNSA Suite), the EU Cyber Resilience Act (CRA), and internal Hardware Cisco Secure Development Lifecycle (HW-CSDL) mandates.
• Author and provide overall direction for hardware security requirements, review checklists, threat models, compliance white papers, and engineering specifications for internal and external consumption.
• Participate in and lead multiple concurrent security evaluations, design reviews, and compliance work streams across diverse hardware programs with a high-level of autonomy.

• Degree in Electrical/Computer Engineering or related field with proven experience: 9+ years (BS), 6+ years (MS), or 3+ years (PhD).
• Prior experience leading security initiatives and mentoring engineers as a technical leader.
• Prior background in hardware development (e.g. reading and interpreting system-level schematics, block diagrams, component datasheets, or register-level hardware documentation).
• Prior background in hardware root-of-trust (RoT), secure boot, hardware or firmware resiliency, tamper resistance, cryptographic imprinting (ECID, etc), or hardware cryptographic acceleration (e.g., AES-GCM, SHA-2/3, LMS/XMSS, ML-DSA/ML-KEM).

• Experience with designing, implementing, or evaluating hardware-rooted attestation architectures and device identity mechanisms (e.g., SPDM, TCG DICE, or IEEE 802.1AR).
• Experience with Hyperscaler and cloud platform architectures (e.g., OCP specifications, OpenBMC, Caliptra, Open Titan, OpenPRoT).
• Experience implementing industry standard security IP or developing novel HW security solutions (e.g. FPGA Bitstream security, secure microcontroller architectures, HW RoT, bus encryption).
• Experience with hardware threat modeling or hardware security analysis (e.g., fault injection, side-channel analysis, JTAG/debug security).
• Prior…