End-to-End FPGA Engineer - VHDL​/DSP​/C++

MDA Space is seeking multiple FPGA‑focused engineers with strong capability across VHDL, DSP/Telecoms, and ideally C++ for embedded parallel processing. This work supports upcoming project wins, with immediate demand expected within 2–4 weeks.

The ideal contractor is someone who can own an FPGA feature end‑to‑end — from requirements capture through to hardware bring‑up — while also contributing to DSP algorithm implementation and, where relevant, C++ development for Versal ACAP AI engines.

• Requirements capture and interpretation for FPGA‑based systems
• Architectural design including block‑level diagrams and interface definition
• MATLAB or Python modelling of mathematical IP blocks
• Development of VHDL test benches for bit‑accurate verification
• Testbench simulation against reference test vectors
• Synthesis, place‑and‑route, and timing closure
• Writing timing constraints and other FPGA constraints
• Hardware bring‑up and validation on target platforms
• Debugging and confirming functionality through hardware test
• (Nice to have) Bare‑metal or Embedded Linux programming to test programmable logic within SoC devices

• Understanding of DSP algorithms commonly implemented in FPGA
• Ability to translate DSP/Telecoms requirements into FPGA architectures
• Experience with modulation, filtering, channel coding, or similar signal‑processing blocks
• (Nice to have) 5G‑specific knowledge for telecoms‑related IP

• C++ development for Versal ACAP AI Engines or similar heterogeneous compute platforms
• Experience with parallel processing, vectorisation, or hardware‑accelerated compute
• Ability to integrate C++ compute kernels with FPGA‑based data paths
• Strong MATLAB experience for algorithm modelling and validation

• Strong FPGA design background with VHDL (not System Verilog)
• Proven experience delivering FPGA features from concept to hardware test
• Ability to write high‑quality test benches and verification environments
• Experience with MATLAB and/or Python for algorithm modelling
• DSP or Telecoms engineering experience
• Understanding of timing closure, constraints, and FPGA tool chains
• Experience with hardware testing, debugging, and validation
• Strong communication skills and ability to work independently in a contract environment