Senior ASIC Verification

Senior IP Verification Engineer

You will be responsible for verification of a design, block or sub‑system, definition and implementation of UVM based test environments, and execution of verification strategy. Your tasks include:

• Break down requirements and create verification specifications, including verification strategy for the design object and associated verification plan
• Develop, run and debug test cases and UVM test benches
• Work with coverage closure to reach quality goals
• Continuously improve and optimize ways of working
• Generate documentation
• Develop competence in technical domain

• A MSc degree in a technical field or equivalent level of education
• 8+ years’ experience in verification using System Verilog and UVM
• Experience in developing verification test plans and directed/randomised test cases
• Good team cooperation skills
• Good communication in English
• Skills in result-driven and meeting expectations

• Experience using Cadence verification suite
• Experience using VManager and VPlans
• Experience from Formal Verification
• Experience in Agile way of working

Principal ASIC Verification Recruitment Specialist