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Senior SoC DV Engineer - Verilog​/UVM & Chip Verification

Job in Cupertino, Santa Clara County, California, 95014, USA
Listing for: Apple Inc.
Full Time position
Listed on 2025-12-01
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading technology company in Cupertino is seeking a Design Verification Engineer to ensure the quality of SOC designs. You will collaborate with teams to develop test plans and methodologies. The ideal candidate will have a Bachelor's degree and over 10 years of experience in digital verification. The role offers a competitive salary and comprehensive benefits, including stock options and educational reimbursement.
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Position Requirements
10+ Years work experience
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