Mask Layout Designer III

Title - Mask Layout Designer III

Location - Cupertino CA

Layout Engineers are responsible for delivering Analog Mixed‑Signal layouts.

They collaborate with Client Layout/schematic DRIs of highly skilled individuals to develop world‑leading SOCs. As a part of the AMS layout team, you will be delivering fully‑verified, layout. This includes the following:

• Crafting sophisticated layout for mixed signal and analog circuits in deep sub‑micron CMOS technologies.
• Reviewing and analyzing floor plans and intricate circuits.
• Running complete sets of design verification tools available on AMS blocks.
• Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed.
• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
• Exceeding engineering specifications and expectations by working closely with the circuit design team.
• Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements.

• 5+ years of experience in analog/mixed‑signal layout design, with a focus on deep sub‑micron CMOS circuits and at least 2+ years in FinFET technologies
• Excellent communication skills and able to work with multi‑functional teams
• Familiar with CAD tools like Virtuoso, Innovus, Calibre is a plus
• Programming knowledge in SKILL, Perl, and/or Python is a bonus
• Concentration in Mixed‑Signal and RF Integrated Circuits is helpful