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Senior ASIC/VLSI Design Engineer - RTL, DFT
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-01-01
Listing for:
Retym Israel Ltd
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment.
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Position Requirements
10+ Years
work experience
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