Physical Design Engineer

• Full-time, 40 hours/week, Permanent position

Physical Design Engineer

Physical Design Engineer

$125,000 – $145,000 per year (commensurate with experience)

USA

40 hours/week, permanent position, full-time

• Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
• Lead the physical design closure process including floor planning, placement, clock tree synthesis, routing, and optimization.
• Develop efficient IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
• Drive implementation of high-performance, low-power, manufacturable designs.
• Perform synthesis, pre-layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
• Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
• Conduct power and area optimization using Multi-Vt, clock gating, and power-aware synthesis.
• Manage post-layout STA, functional/timing ECOs, and high-frequency IP designs closure.
• Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign-off standards.
• Collaborate with cross-functional teams to resolve design and manufacturing issues.
• Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
• Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, Prime Time) for implementation and signoff readiness.

• Mentor junior engineers and review design outputs.
• Document physical design flows, constraints, and reports.
• Implement and improve methodologies, workflows, and tools for better process quality and efficiency.

Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.

Must be able to travel/relocate to various client sites across the U.S.

Neetha Consulting LLC
10080 North Wolfe Road, Suite SW3-200

Cupertino, CA 95014