ASIC Design Engineer – SystemVerilog RTL Perf HW
Listed on 2026-10-16
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Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Annapurna Labs (U.S.) Inc. in Cupertino, CA is hiring for an ASIC II to design and optimize hardware in data centers, including AWS Inferentia. You will develop high-performance RTL designs and System Verilog implementations to meet strict power and area targets.
Responsibilities include linting and timing checks, collaborating with architects, verification teams, and back-end experts. Requires a Bachelor's in CS/Engineering and 3 years of relevant experience.
This opportunity is for the ASIC Design Engineer – System Verilog RTL for High Perf HW role at Amazon.
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We would love to welcome a new ASIC Design Engineer – System Verilog RTL for High Perf HW to our group in Cupertino, CA, United States.
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