SerDes Design & Validation Engineer Speed IP Leader
Listed on 2026-10-16
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Engineering
Electronics Engineer, Test Engineer, Quality Engineering
Apple Inc. is seeking a Ser Des Design and Validation Engineer in Cupertino to lead system validation of mixed-signal Ser Des IP. You will design, integrate and validate high-speed analog/mixed-signal blocks, develop test plans, and drive production test readiness with design teams.
A strong background in Ser Des, DFT, and AMS IC development is required, with a track record of lab testing and data analysis. The role emphasizes collaboration, innovation, and driving silicon success across
This is a genuine role to take on the Ser Des Design & Validation Engineer — High‑Speed IP Leader role at Apple Inc.
All applications are reviewed carefully by our team.
The position is based in Cupertino, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 129..
We aim to respond to suitable candidates as soon as possible.
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