FE Engineering

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Deliver complex digital IPs for Power Management ICs (PMICs), meeting schedule, area, power, and performance targets. Perform RTL design in System Verilog for digital control logic, including the implementation of FSMs and other control structures. Collaborate with cross-functional teams, including Analog Design, Architecture, DFT, and ATE, to develop and finalize precise design specifications.

Synthesize RTL designs into gates and analyze Power, Performance, and Area (PPA) impact using industry-standard tools such as Synopsys Design Compiler, Cadence Genus, and Prime Time PX. Apply low-power design techniques, including clock and power gating. Perform RTL simulation and functional verification using tools like Cadence Xcelium and Simvision to assess waveforms and ensure correct functionality. Collaborate with the verification team to ensure RTL code meets all feature requirements as defined in the specifications.

Perform Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and verification. Manage general design signoff duties, including the cleanup of SDC, CDC, and other constraints files. Utilize scripting languages like Perl and Python for ASIC flow development tasks. Support the Silicon Validation team by explaining design functionality, reviewing test plans, and providing debugging assistance Collaborate with managers and program managers to track project progress.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS:
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including:
Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits:  Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Experience and/or education must include:
• Designing digital logic in ASIC using System Verilog to implement specific functionalities and features for the ASIC’s required behavior.
• Simulating ASIC designs using Cadence or Synopsys System Verilog Simulators to verify functional correctness and identify design flaws early before tape out.
• Analyzing circuit behavior in…