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Physical Design Engineer

Job in Cupertino, Santa Clara County, California, 95014, USA
Listing for: Apple Inc.
Full Time position
Listed on 2026-10-18
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 174149 - 225300 USD Yearly USD 174149.00 225300.00 YEAR
Job Description & How to Apply Below

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Analyze and perform static and dynamic power reduction of the advanced node technology and complex SoC design. Implement the low power design techniques and meet the power target goals. Perform critical ECOs (Engineering Change Orders) to fix the identified violations from the analysis of all design aspects, such as Timing, Physical verification, Power Grid integrity, and Logic equivalent checks for design closure for tape out.

Perform scripting and programming for CAD tool flow development for automation problem solving and efficiency improvement. Execute chip/partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve design power, performance and area. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.

Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improving design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role.

The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS:
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including:
Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits:  Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications
  • Master's degree or foreign equivalent in Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
  • Experience and/or education must include:
  • 1. Utilize Innovus or Fusion Compiler APR tools to perform implementation design, including applying these tools in physical design workflows and supporting execution of implementation design tasks.
  • 2. Tune implementation design flows and methodologies to improve the power, performance, and area of designs.
  • 3. Perform static timing analysis and apply timing convergence techniques, conduct IR/IVD analysis, implement violation fixes, and debug and resolve LVC/DRC violations.
  • 4. Perform physical design on advanced technology nodes (7nm and below), with knowledge of modern CMOS technology and…
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