SoC Power Modeling Engineer – Optimize AI/ML & IPs
Listed on 2026-11-04
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Engineering
Test Engineer, Electrical Engineering, Systems Engineer
Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.
You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.
This is an excellent opening to take on the SoC Power Modeling Engineer – Optimize AI/ML & IPs role at Apple Inc.
We would love to welcome a new SoC Power Modeling Engineer – Optimize AI/ML & IPs to our group in Cupertino, CA, United States.
For the SoC Power Modeling Engineer – Optimize AI/ML & IPs position at Apple Inc., we are reviewing applications now.
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