SoC DV Engineer - Verilog, UVM & Testbench Expert

Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.

You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/System Verilog, digital design fundamentals, and scripting (Python/Perl).

We are seeking a motivated SoC DV Engineer
- Verilog, UVM & Testbench Expert to join Apple Inc. in Cupertino, CA, United States.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the SoC DV Engineer
- Verilog, UVM & Testbench Expert role in the description above.

We appreciate your interest in this position.

Join Apple Inc. and contribute to our ongoing work.