Senior Principal Digital Design Engineer

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Location:

Cypress, CA, US, 90630

Job :112742

Location:

Cypress CA onsite

Schedule:

9/80

The Electro Optical Infrared Systems (EOIS) line of business within DRS has locations in Dallas and Austin, TX, Melbourne, FL, and Cypress, CA. EOIS develops, manufactures, and supports infrared and electro-optical solutions for soldiers, ground vehicles and airborne platforms. We offer an exciting and challenging work environment, a competitive salary and benefits package, and a business culture that rewards performance.

Employing the world’s brightest. Supporting the world’s bravest.

DRS Network & Imaging Systems in Cypress, CA is part of the Electro-Optical and Infrared Systems Group of Leonardo DRS and has over 30 years of experience in designing and developing electro-optical/infrared systems for surveillance and targeting applications. We are seeking a Senior Principal Digital Design Engineer to join the company in the development of strategic space and weather systems.

• Bachelor’s or Master's degree in electrical engineering or related technical field with a minimum of 10 years of experience working in Electrical Engineering with emphasis in FPGA design
• Ability to solve problems at circuit and system levels
• Proven experience with FPGA development, including VHDL or Verilog programming
• Excellent written and oral communication skills, ability to provide and receive constructive criticism
• Ability to lead major problem resolution efforts and support regaining or attaining customer partner status
• Demonstrated ability to execute large group and customer presentations
• Ability to work and collaborate effectively in a team as well as independently
• Action-oriented and eager to embrace new opportunities and tough challenges with a sense of urgency, high energy, and enthusiasm

• 15+ years of experience working in Electrical Engineering with emphasis in FPGA design
• Proficient in the design and analysis of FPGAs for space applications
• Experience with EO/IR technology
• Skilled in the design and troubleshooting of high-speed video applications
• Familiarity with DoD, NASA, and relevant industry standards
• Current Secret or Top Secret (TS) clearance

• In this role, you will be responsible for completing FPGA development from concept through to production, including architecture definition, design, simulation, and verification
• Develop low-power high-speed interfaces for imaging payloads
• FPGA Design, system simulation, synthesis, resource and power utilization analysis, place and route, timing analysis, verification, and integration activities
• Block level and chip level simulations to verify functionality and performance goals
• Hardware debugging and integration using standard test equipment including oscilloscope, power supply, multi-meter, etc.
• Create documentation such as board specifications, user guides, test reports, and design review presentations
• Provide regular reporting of progress and status
• Responsible for completion of assigned task on time and meeting technical requirements
• Specify and evaluate supplier components, subsystems, and services
• Support, communicate, reinforce, and defend the mission, values, and culture of the organization
• Attend appropriate engineering, customer, or business meetings
• Mentor and coach less-experienced engineers

Normal for an office environment. Work may require occasional weekend and/or evening work and local travel.

U.S. Citizenship required. This position requires an active DOD security clearance or the ability to obtain such clearance within a reasonable time after commencement of employment.

The expected pay scale for this position is $159,298/year - $247,310/year. Should the level, location, or scope of the position change during the hiring process, the pay scale may be modified accordingly. When extending an offer of employment, Leonardo DRS considers factors such as (but not limited to) the scope and responsibilities of the position; any Federal Government contract labor categories and contract wage…