Resolution Enhancement Techniques Process Development Engineer

Resolution Enhancement Techniques Process Development Engineer

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As a Resolution Enhancement Techniques (RET) modeling engineer, you’ll create and optimize OPC models for Texas Instruments’ most advanced technology nodes, including lithography and etch‑based models.

• Partner with design, process engineering and integration teams to define the design shapes needed for accurate model building.
• Design parameterized mask layouts necessary for model inputs.
• Investigate and implement ML and AI methods to improve model accuracy and runtime.
• Implement advanced optimization techniques.
• Collaborate with process engineering and integration teams on wafer verification to validate model quality.
• Work with OPC verification engineers to enhance post‑OPC verification models such as weak image, assist feature printing, and resist top‑loss models.
• Troubleshoot photolithographic patterning issues related to OPC modeling across all TI fabs.
• Develop and maintain a suite of model quality checks for unit testing, including grid checks, stability tests, OPC convergence tests, and ghost contour checks.
• Develop models that support multi‑patterning approaches such as SADP and LELE.

• Master’s degree in Electrical Engineering, Physics, Computer Science, Chemistry or a related field.
• 10+ years of experience in OPC modeling in advanced node lithography.
• Expertise in selecting and optimizing features for accurately sampling design spaces.
• Expertise in developing test requirements to validate OPC modeling solutions.
• Strong knowledge of advanced lithography simulation and RET techniques used in semiconductor manufacturing.

• Ability to lead and drive advanced processes for double‑patterning techniques in 22 nm node development.
• Expertise with Synopsys Pro Gen modeling software.
• Demonstrated knowledge of OPC verification packages such as ORC, LMC+, or PLRC.
• Knowledge of critical parameters for 28 nm and 22 nm node processing.
• Familiarity with physical layout (gds/oas) and litho/OPC test pattern design using Cadence Virtuoso or KLayout.
• Programming experience in Unix environments.
• Understanding of OPC pattern validation methodologies and process window assessment techniques (e.g., KLA Photolithography Wafer Qualification).
• Strong analytical and problem‑solving skills.
• Excellent verbal and written communication skills.
• Team‑oriented collaboration across functions.
• Effective time‑management and on‑time project delivery.
• Ability to build influential relationships and work in fast‑paced, rapidly changing environments.
• Strong initiative and drive for results.

Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips. TI is an equal‑opportunity employer and supports a diverse, inclusive work environment. All qualified applicants receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.