Ethernet IP Design Verification Engineer

Job Description

Talent 101 seeks an experienced Ethernet IP Design Verification Engineer for a contract semiconductor engineering engagement. The engineer will be responsible for verification of networking/Ethernet IP, development and execution of verification plans, testbench and testcase development, functional coverage, regression analysis, and debugging.

The ideal candidate has directly verified Ethernet or closely related networking IP at the ASIC/IP level and understands Ethernet protocol behavior, packet traffic, interfaces, corner cases, error conditions, and performance-oriented verification. This position requires more than general ASIC verification experience; practical Ethernet/networking IP DV experience is a key qualification.

• Develop and execute verification plans for Ethernet and networking IP blocks.
• Build, enhance, and maintain System Verilog/UVM verification environments.
• Develop directed and constrained-random testcases for networking functionality.
• Generate and verify Ethernet packet traffic across supported interfaces and operating modes.
• Develop checkers, scoreboards, monitors, assertions, functional coverage, and verification components.
• Verify protocol behavior, packet handling, configuration, control/status paths, error handling, and corner cases.
• Run regressions, analyze failures, debug waveforms, and identify root causes in RTL, testbench, or verification infrastructure.
• Work closely with RTL designers and architects to clarify requirements and resolve design issues.
• Measure functional and code coverage and drive verification closure.
• Reuse and modify existing verification IP and testbench components where appropriate.
• Support IP-level and, when required, subsystem/SoC-level integration verification.
• Document verification results, open issues, coverage status, and test completion.

• Strong ASIC or semiconductor design verification experience.
• Hands-on verification experience with Ethernet or networking IP.
• Strong System Verilog and UVM experience.
• Experience developing verification plans and testcase strategies from specifications.
• Experience building or modifying UVM test benches, sequences, drivers, monitors, scoreboards, and coverage models.
• Strong constrained-random verification and functional coverage experience.
• Strong regression debugging and waveform-analysis skills.
• Understanding of Ethernet frames, packet processing, protocol behavior, and networking concepts.
• Ability to debug interactions between RTL and verification environments.
• Experience working closely with RTL designers, architects, and other verification engineers.

• Experience with Ethernet MAC, PCS, PHY-facing interfaces, or related networking IP.
• Knowledge of IEEE 802.3 Ethernet standards and relevant protocol features.
• Experience with multiple Ethernet speeds or high-speed Ethernet designs.
• Experience with packet generators, protocol VIP, or Ethernet verification IP.
• Experience with common interfaces such as MII/GMII/XGMII or comparable Ethernet interfaces.
• Experience with assertions/SVA and formal or assertion-based verification.
• Experience with IP-to-SoC integration verification.
• Python, Perl, Tcl, shell, or other scripting experience for automation and regression analysis.
• Experience with gate-level simulation or post-silicon correlation is beneficial.

Talent 101 is a global services provider for the semiconductor industry only. We provide a total workforce or project turnkey solution anywhere you need it: onshore, nearshore, or offshore.

Talent 101 is a global services provider for the semiconductor industry only. We provide a total workforce or project turnkey solution anywhere you need it: onshore, nearshore, or offshore.