Digital Design Engineer; RTL

Job Description

Explore Your Career Possibilities

At Talent
101, your talent can make a difference. We connect skilled engineering and technology professionals with challenging opportunities where their expertise has a direct impact.

As part of a Talent
101 managed services team, you’ll work alongside talented professionals, solve real-world engineering challenges, and support innovative projects for some of the world’s leading technology companies.

We look for people who are passionate about what they do, bring their best every day, and want the opportunity to grow while making a meaningful contribution.

Bring your expertise. Make an impact. Build what’s next with Talent
101.

We are expanding our Managed Services team and seeking a Digital Design Engineer (RTL) with experience in Intellectual Property (IP) development and Verilog-based RTL design. This is an onsite position in Dallas, Texas.

Responsibilities may include, but are not limited to:

· Architect and implement synthesizable RTL in Verilog for high-speed I/O subsystems and high speed Ethernet MAC/PHY blocks.

· Develop custom IP blocks and modify existing Synopsys Design Ware IPs to meet performance, area, and power targets.

· Ensure RTL adheres to design specifications, protocol standards (e.g., IEEE 802.3), and integration requirements.

· Integrate third-party IPs (e.g., Synopsys USB, PCIe, Ethernet) into SoC environments, customizing interfaces and configuration parameters.

· Collaborate with system architects to align IP functionality with broader system-level goals.

· Resolve compatibility issues across clock domains, reset strategies, and bus protocols (e.g., AXI, AHB).

· Translate high-level architectural requirements into detailed microarchitecture specs.

· VFS in for converter IC’s DC-DC Op-Amp. Buck, Boost etc.

· Define Datapath, control logic, and FSMs for high-throughput, low-latency designs.

· Document design intent, interface definitions, and configuration registers.

· Work closely with verification teams to define test plans, support UVM testbench development, and debug RTL issues.

· Collaborate with physical design teams to support synthesis, floor planning, and timing closure.

· Participate in timing analysis, linting, and formal checks to ensure design robustness.

· Analyze and optimize RTL for timing, area, and power using Synopsys tools (Design Compiler, Prime Time).

· Implement pipelining, clock gating, and resource sharing techniques to meet stringent performance goals.

· Support post-silicon validation and correlate lab measurements with pre-silicon simulations.

· Maintain version-controlled RTL repositories and follow structured design handoff procedures.

· Use scripting (Python, Tcl, Perl) to automate design tasks, IP configuration, and build flows.

· Contribute to continuous improvement of design methodologies and internal IP libraries.

· Interface with firmware, AMS, and system integration teams to ensure seamless end-to-end functionality.

· Participate in design reviews, spec discussions, and bring-up planning for tape-out and silicon validation.

· Provide technical guidance and mentorship to junior engineers on RTL best practices and IP reuse strategies.

Qualifications – Minimum Requirements:

• 7+ years Digital Design experience of complex high speed IO sockets
• Solid foundation in digital logic design, computer architecture, and communication systems.
• Proficiency in Verilog (and optionally System Verilog) for synthesizable RTL design.
• Experience in custom IP development and modification of Synopsys Design Ware IPs, including configuration, integration, and optimization.
• Familiarity with IP-XACT, IP packaging standards, and SoC integration flows
• Strong understanding of high-speed interface protocols such as PCIe, USB,…