Senior FPGA Design Engineer - 25G/100G Versal Space
Listed on 2026-10-25
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Engineering
Hardware Engineer, Electronics Engineer
Job Title:
Senior FPGA Design Engineer
About The Program:
Our client is building one of the world's largest low-Earth-orbit satellite constellations, delivering broadband internet from space. The hardware team behind it designs the electronics that drive the satellites' phased-array antennas: meter-scale, 20+ layer boards carrying custom silicon connected by ~25 Gbps high-speed serial links. Boards are designed, brought up, and validated in-house - engineers on this team see their own work running on real flight hardware.
The Role:
You will own programmable logic in the phased-array signal chain on AMD/Xilinx Versal devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.
What You'll Do:
Design, integrate, and debug RTL for high-speed datapaths on Versal ACAP devices.
Configure and bring up GTY transceivers - link tuning, eye scans, and debug of live 25 Gbps-class serial links.
Configure MRMAC hard IP for multi-rate Ethernet (25G / 50G / 100G) and validate high-rate traffic end to end.
Build and maintain embedded Linux (Peta Linux/Yocto) images, device trees, and drivers for the Versal processing system.
Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers.
Build debug and monitoring hooks used across design validation campaigns.
Required Experience:
25G/50G/100G
- Very high speed interfaces - hands-on design and bring-up at 25G / 50G / 100G.
MRMAC & GTY
- Direct experience configuring MRMAC and GTY blocks - transceiver setup, tuning, and link debug on real hardware.
Versal ACAP
- Working knowledge of the Versal ACAP architecture and toolchain (Vivado/Vitis).
Embedded Linux
- Building images, device trees, and drivers for ARM-based FPGA processing systems (Peta Linux/Yocto).
8+ years of RTL design (Verilog/System Verilog/VHDL) shipped in real products, with timing closure on modern devices and genuine board bring-up experience.
Nice To Have:
JESD
204, Aurora, or other high-speed converter/serial protocols.
Aerospace or high-reliability design exposure (DO-254, MIL-STD, radiation-aware design).
Prior satellite, SATCOM, radar, or high-speed networking product work.
Experience prototyping functions ahead of custom ASIC development.
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