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Team Lead Digital Verification
Job in
2600, Delft, South Holland, Netherlands
Listed on 2026-05-25
Listing for:
Qualinx B.V.
Full Time
position Listed on 2026-05-25
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Who are we?
At Qualinx, we’re not just building chips; we’re engineering the future fabric of the connected world. As a pioneering semiconductor scale‑up, we’re transforming how devices connect, communicate, and operate through our ground‑breaking Digital RF technology. Our mission goes beyond ultra‑low power GNSS; we’re redefining what’s possible in adaptive, scalable, and intelligent connectivity for the Internet of Things.
What Sets Us Apart
We hold ourselves to high standards, thrive on solving the unexpected, and push boundaries together. Our culture blends curiosity, team spirit, and a touch of unconventional charm, creating a fast‑paced, meaningful environment.
Job Description
As a Team Lead Digital ASIC Verification Engineer you will shape the future of our technology. You will verify digital IP blocks, simulate and post‑layout SoC chip‑level models, and contribute to circuit design.
Lead ASIC verification using System Verilog and UVM.
Simulate and verify digital RTL blocks, including state machines, DSP, and multi‑clock‑domain interfaces.
Conduct post‑layout simulation of complex mixed‑signal SoCs.
Develop test benches and test cases for block‑level functional verification.
Collaborate with backend and implementation teams on synthesis, timing, and DFT issues.
Support design integration activities like lint, CDC, synthesis, and ECO.
Define verification plans, run regressions, reproduce, and debug functional and performance bugs.
Verify various IPs/Sub‑IPs integrated into the top‑level SoC.
Assist design synthesis and fix timing issues for the physical design team.
Requirements
Bachelor’s degree or higher in Electrical Engineering.
10+ years of experience as an ASIC Verification Engineer.
At least a few years as a team lead.
Proficiency with EDA tools and design languages, including Verilog.
Experience with standard EDA tools such as Cadence and Mentor.
Experience designing complex mixed‑signal products with analog blocks and microcontrollers.
Background in RTL and ultra‑low‑power designs; knowledge of digital design flow from architecture to sign‑off.
Understanding of synthesis, static timing analysis, and netlist verification.
Experience in digital backend flow for floor planning and Place & Route.
Knowledge of digital DFT/ECO flows.
Strong programming skills in MATLAB, C/C++, Tcl.
Experience setting up power‑distribution architecture, power‑intent specification and validation methodology.
Strong knowledge of clock‑domain‑crossing techniques.
Knowledge of ASIC test methodology (scan insertion, memory BIST, test‑pattern generation).
Strong analytical and problem‑solving skills.
Benefits
Employee equity and potential ownership.
Wellness resources, including company discounts and a free mental healthcare platform.
Visa support for relocating candidates.
Pension contributions.
Modern, vibrant workspace.
Quarterly team events.
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