Senior Analog IC Layout Engineer

Location: The Hague

Position Overview  I am recruiting for a Senior IC Layout Design Engineer to join my client's design centre near Delft, Netherlands.

Key Responsibilities   Top-level and block-level layout for analog and digital blocks
Schematic driven layout and constraint-based design
Chip level floor planning, power distribution, shielding and device matching
Layout verification including DRC, LVS and ERC
Chip-level integration and support for tape-out
Training and guidance for junior and offshore layout engineers
Collaboration across multiple global design centres
Key Requirements   6 to 12 years of experience in layout design for analog and digital circuits
Strong background in CMOS and BiCMOS, ideally including TSMC 180nm, 65nm and 22nm nodes
Proficient with Cadence Virtuoso and familiar with DRC/LVS/ERC tools (PVS or Calibre)
Solid understanding of layout effects including parasitics, matching, EM, IR drop and crosstalk
Familiarity with layout automation and scripting tools is a plus
Additional Information  My client offers a collaborative working environment with technically challenging projects, and the opportunity to influence layout practices company-wide.
This job requires five days on site.

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