AMS Verification Engineer; UVM​/SV - CMOS - s

Position: AMS Verification Engineer (UVM/SV) - CMOS - Visas Supported”
Location: The Hague

A fantastic opportunity for an experienced Verification Engineer to join a market leading Semiconductor company, who specialise in MEMS precision timing.

This role will be performed alongside the team in Delft (The Netherlands), and the company can offer Visa and Relocation Support where required.

Responsibilities

Developing SV-RNM models for both analog and mixed-signal circuits

Developing verification plan from chip or block specifications

Defining and writing System Verilog Assertions (SVA)

Defining and writing functional coverages and cover groups

Running simulations and debugging simulation results

Reviewing verification results for Tape-out sign-off

Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas.

Bachelors degree in electrical/computer engineering or related fields with 6 years of work experience doing verification in the semiconductor industry

Proficient in System Verilog and System Verilog OOP

Fluency in utilizing scripting languages such as Perl / Python

Proficient (through work experience) in verification using UVM

Strong experience writing System Verilog Assertions (SVA)

Understanding of Analog schematic and experience with Cadence Virtuoso

Basic understanding of digital design using Verilog

Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers

By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice ()

#J-18808-Ljbffr