ASIC​/FPGA Principal SoC Engineer VI

Job Title

ASIC/FPGA Verification Engineer

This position is fully remote; preferred candidate will be expected to work a flexible 9x80 schedule.

Lockheed Martin is dedicated to keeping people safe and solving the world's most complex challenges. We provide diverse career opportunities and competitive pay with comprehensive benefits.

We are building the best SOC team at Lockheed Martin Space's Silicon Solutions team and seeking a Principal SoC Engineer who will improve speed and efficiency of the verification/validation of ASICs, FPGAs, and SOCs.

As the Principal SME for SoC development, you will support all aspects of ASIC, FPGA, and SoC development, partner with verification engineers, and provide recommendations for devices, process, tools, suppliers, and talent.

• Mentor others in verification and validation best practices.
• Continuously assess new tools and methodologies, present findings, make recommendations, and train others.
• Drive methodologies and automation to deploy rigorous processes focusing on CI pipelines, quality monitoring, and consistent deployment across programs.
• Work closely with design and verification teams to develop cohesive solutions.
• Develop business cases that support SoC development improvements.
• Support technical reviews and present to internal and external stakeholders.
• Work directly with programs to provide achievable SOC solutions.

• 12+ years of professional experience.
• Strong business acumen and soft skills in presenting and training for technical concepts.
• Will obtain and maintain a DoD Top Secret clearance and is a US Citizen.

• Bachelor of Science or higher in Electrical Engineering or related discipline, or equivalent experience.
• Experience in requirements capture, architecture, design, and implementation of complex SoCs based on mission and system CONOPS.
• Experience with methodologies and tools for implementing SoC designs into AMD Versal, Microchip Polar Fire SoC, and/or fully custom ICs with processors.
• Experience in ASIC/FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
• Experience leading projects of multiple engineers, managing schedules, prioritizing work, and communicating with stakeholders.
• Experience driving process advancement and program reviews.
• HDL programming expertise with VHDL, System Verilog, and/or Verilog.
• Experience mentoring and training other engineers.
• Experience presenting to customers and executive leadership.
• Will obtain and maintain a DoD Top Secret clearance and is a US Citizen.

• Experience in modern ASIC/FPGA/SoC verification strategies such as UVM/System Verilog, emulation, formal verification, and lab-based techniques.
• Experience or coursework in hardware emulation (ZeBu, Palladium, etc.).
• Experience in microelectronics radiation mitigation techniques for space applications.
• Experience in foundry and packaging technologies including wafer, device, and package test and assembly.
• Experience scripting such as Perl, TCL, Python.
• Experience with MS Project, JIRA, and Earned Value Management System (EVMS).

This position requires a government security clearance; you must be a US Citizen.

The annual base salary range for this position varies by state and location. For example, in California, Massachusetts, New York (excluding major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington, or Washington DC it is $170,900 – $301,415. For states not referenced above, the salary range reflects the candidate's final work location.

Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays.

Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.

The application window will close in 90 days; applicants are encouraged to apply within 5–30 days of the requisition posting date.