FPGA and Signal Processing Sr Manager - Lunar Permanence

FPGA and Signal Processing Sr Manager - Lunar Permanence

Join to apply for the FPGA and Signal Processing Sr Manager - Lunar Permanence role at Blue Origin

Applications will be accepted on an ongoing basis until the requisition is closed.
At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low‑cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!
This role is part of the Lunar Permanence business unit, which develops Blue Origin’s Blue Moon landers and related products. To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are building sustainable infrastructure for our transport of crew and cargo from Earth to the lunar surface.

• Lead, mentor, and manage a team of FPGA and DSP engineers, including conducting performance reviews, setting career development plans, and facilitating ongoing training.
• Provide technical guidance and oversight throughout the entire FPGA development lifecycle, from architecture definition and requirements gathering to implementation, verification, and validation.
• Define and enforce standardized design methodologies, coding standards, and quality assurance processes across all FPGA projects.
• Drive continuous improvement within the team by assessing and evaluating new tools, design techniques, and emerging FPGA technologies.

• Manage project schedules, budgets, resource allocation, and technical risks to ensure timely and on‑budget delivery of FPGA and DSP solutions.
• Present project status updates, design reviews, and technical findings to both internal stakeholders and external customers.
• Coordinate with other engineering teams—including hardware, software, and systems engineering—to define requirements and manage interfaces.

• Direct the architecture and design of FPGA‑based solutions for high‑performance, real‑time digital signal processing applications.
• Oversee the implementation of signal processing algorithms such as filters, FFTs, and modulation/demodulation on FPGA platforms.
• Ensure designs meet stringent requirements for performance, area, power efficiency, reliability, and security.
• Drive the selection and evaluation of appropriate FPGA devices, IP cores, and associated tool chains.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

• Minimum of 8+ years of experience in FPGA design and digital signal processing.
• Minimum of 5+ years of experience in technical leadership or management.
• Proven experience delivering complex FPGA solutions for real‑world products.

• Deep expertise in digital design, FPGA architecture, and design tradeoffs.
• Proficiency with Hardware Description Languages (HDLs) such as VHDL and Verilog/System Verilog.
• Strong knowledge of digital signal processing (DSP) theory and implementation techniques including FFT, FIR, and adaptive filters.
• Expertise with FPGA vendor tool chains (e.g., AMD/Xilinx Vivado, Intel/Altera Quartus).
• Experience with high‑speed digital interfaces (e.g., PCIe, DDR4, 10/40/100 GbE) and embedded processors on FPGAs (SoC).
• Knowledge of standard verification methodologies (e.g., UVM) and tools (e.g., Questa Sim/Model Sim or equivalent).
• Familiarity with lab bring‑up, debugging tools (e.g., ILA), and high‑speed test equipment.

• Exceptional leadership, communication, and interpersonal skills.
• Strong problem‑solving, analytical, and critical thinking abilities.
• Proven ability to work effectively in a cross‑functional team environment.

• Experience with high‑level synthesis (HLS) tools.
• Knowledge of specific application areas, such as communications, radar, software‑defined radios, or embedded systems.
• Familiarity with version control systems (e.g., Git) and project tracking software (e.g., Jira).

CO applicants: $ – $. WA applicants: $ – $.…