Engineer, Test Engineer

Imec Qatar is a new regional office where we drive our mission of pioneering innovative semiconductor solutions that lay the foundation for a smarter, greener, and truly AI-driven future. Specializing in advanced design tools for emerging technologies like silicon photonics and 3D integrated circuits, imec Qatar is at the forefront of chip development. We are also driving the future with intelligent solutions to optimize infrastructure and deep-tech innovations targeting applications for a sustainable society.

This is more than just a new office - it is the start of an exciting journey. With the launch of imec Qatar, you have the unique opportunity to join us from day one and help shape the future of semiconductor innovation in the region. Be part of the team from the very beginning, joining us as DFT Engineer in Doha, Qatar.

As a DFT Engineer, you leverage your expertise in Design-for-Test to make cutting-edge integrated circuits optimally testable. Working at the forefront of semiconductor technology, you play a pivotal role in ensuring the testability, quality, and performance of complex chip designs. You will:

• Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft/hard IPs with complex DFT requirements.
• Coordinate/Negotiate DFT requirements.
• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/R(epair) and On-chip clock controllers for large-scale low-power designs in advanced nodes (5nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues.
• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.
• Work closely with the test engineering team on silicon characterization and validation.
• Adopt AI methodology to speed up all aspects of your work.

• 5+ years of experience with DFT insertion and ATPG.
• Basic fluency with Verilog/VHDL to write code for test logic when needed.
• Experience as a DFT owner of sub-systems including the insertion and verification of all DFT structures.
• Experience with DFT integration of complex PHY blocks (such as PCIe, UCIe, LPDDR5, etc.).
• Hands‑on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug, for large low‑power designs in advanced nodes (5nm and beyond).
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).
• Preferably previous experience with defining/maintaining DFT flows.
• Experienced in EDA tools such as Tessent (Siemens), Genus/Modus (Cadence), and simulation tools.
• Experience using Tessent SSN is a plus.
• Experience with the IEEE
  1838 standard and DFT for chiplets (2.5D/3D) is a plus.
• Experienced in scripting languages, especially TCL.

You will join a world-class research center in nanotechnology at our brand-new office in Doha, Qatar. You will be part of a team that shapes technology that will determine the society of tomorrow. Imec is an inclusive employer with an open, multicultural, and informal working environment. We provide ample room for initiative and professional development.

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee‑based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.