DFT Engineer
Listed on 2026-10-28
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer, Electrical Engineering
What you will do As a DFT Engineer you leverage your expertise in Design-for-Test to make cutting-edge integrated circuits optimally testable Working at the forefront of semiconductor technology you play a pivotal role in ensuring the testability quality and performance of complex chip designs You will Architect DFT solutions for SOCs with multiple sub-blocks partitions and complex soft hard IPs with complex DFT requirements Coordinate Negotiate DFT requirements Implement and validate innovative DFT techniques on SOCs and sub-systems Define timing constraints for DFT test-modes Insert boundary scan compression MBIST R epair and On-chip clock controllers for large-scale low-power designs in advanced nodes 5nm and beyond Generate test patterns debug improve fault coverage support debug of post-silicon test patterns diagnose memory and scan issues Work closely with the physical design team in the context of timing violations signal power integrity issues routing congestion etc Work closely with the test engineering team on silicon characterization and validation Adopt AI methodology to speed up all aspects of your work
Who you are- 5+ years of experience with DFT insertion and ATPG.
- Basic fluency with Verilog/VHDL to write code for test logic when needed.
- Experience as a DFT owner of sub-systems including the insertion and verification of all DFT structures.
- Experience with DFT integration of complex PHY blocks (such as PCIe, UCIe, LPDDR5, etc.).
- Hands-on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug, for large low-power designs in advanced nodes (5nm and beyond).
- Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).
- Preferably previous experience with defining/maintaining DFT flows.
- Experienced in EDA tools such as Tessent (Siemens), Genus/Modus (Cadence), and simulation tools.
- Experience using Tessent SSN is a plus.
- Experience with the IEEE
1838 standard and DFT for chiplets (2.5D/3D) is a plus. - Experienced in scripting languages, especially TCL.
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