Physical ASIC Design Implementation Engineer

Imec Qatar is a new regional office where we drive our mission of pioneering innovative semiconductor solutions that lay the foundation for a smarter greener and truly AI-driven future Specializing in advanced design tools for emerging technologies like silicon photonics and 3D integrated circuits imec Qatar is at the forefront of chip development We are also driving the future with intelligent solutions to optimize infrastructure and deep-tech innovations targeting applications for a sustainable society This is more than just a new office - it is the start of an exciting journey With the launch of imec Qatar you have the unique opportunity to join us from day one and help shape the future of semiconductor innovation in the region Be part of the team from the very beginning joining us as Physical ASIC Design Implementation Engineer in Doha Qatar

• Imec s digital chip design team handles all steps from architecture to chip tapeout to the foundry
• For the further extension of the physical digital implementation group we are looking for a highly motivated engineer
• The international team has an extensive industrial experience contacts with leading industrial foundries and long-standing relationships with all the main EDA tool vendors and IP providers
• Imec also provides tapeout prototype fabrication and test services for advanced chips
• As Physical ASIC design engineer you will create GDSII files that can be sent to production from RTL or netlist
• You will have full understanding of the complete Place amp Route flow
• You Will Set up the flow for the specific library set and foundry node used
  
  Set up low power design UPF Floor planning amp power grid design
• Detailed Timing Driven PlacementSTA amp possible design optimisation for setup
  
  Clock Tree Synthesis Scan chain re-stitching
  
  Detailed Timing Driven Route incl SI IPO s in-place optimization to get the timing in all corners correct
• Solve setup amp hold violations
  
  Sign-off extraction
  
  Sign-off timing
  
  Sign-off Power analysis
  
  Physical verification DRC ERC LVS ANT Logic equivalent check
• It it is an asset if you can take the lead for partitioning and split the top level SDC file into timing budget requirements constraints of the sub-blocks for hierarchical design
• You Will work with other Physical Designers during the chip design cycle to drive signoff closure for tape-out
• You are also looking out for AI methodology in the design flow to speed up all aspects of your work

• You have a Master Degree in Electronics
• You have experience in hierarchical physical implementation in advanced nodes with either a Synopsys or Cadence EDA tool fow.
• You have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains.
• You have experience in debugging any tool/flow/design issues.
• You have excellent communication skills (English is a must) and can work within an international team.