RISC-V CPU Power and Performance Modelling 's Semiconductor Technologies
Listed on 2026-10-31
-
Engineering
Electronics Engineer, Systems Engineer, Research Scientist, Hardware Engineer
RISC-V CPU Power and Performance Modelling for imec’s Future Semiconductor Technologies References
[1] M. Brunion et al ., "CMOS 2.0 - Redefining the Future of Scaling," 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD) , Munich, Germany, 2025, pp. 1-8, doi : 10.1109/ICCAD
[2] S. Li, J. H. Ahn, R.
D. Strong, J.
B. Brockman,
D. M. Tullsen and N. P. Jouppi, " McPAT :
An integrated power, area, and timing modelling framework for multicore and manycore architectures," 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) , New York, NY, USA, 2009, pp. 469-480.
[3] Lakshminarasimhan, Kartik, et al. "The forward slice core microarchitecture." Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques . 2020.
[ 4 ] S. Palacharla , N. P. Jouppi, and J.
E. Smith, “Complexity-Effective Superscalar Processors,” ISCA 1997. [ 5 ]
D. Folegnani and
A. González, “Energy-Effective Issue Logic,” ISCA 2001. [ 6 ] I. Park,
C. L. Ooi, and T. N. Vijaykumar, “Reducing Design Complexity of the Load/Store Queue,” MICRO 2003.
Type of internship
:
PhD internship, Master internship
Duration
: 6 - 9 months
Required educational background
:
Electrotechnics/Electrical Engineering, Computer Science
The reference code for this position is 2026-INT-336
.
Imec allowance will be provided.
Objectives- Develop and evaluate technology-aware RISC-V CPU microarchitecture models
- Correlate key microarchitectural structures with equivalent RTL implementations
- Characterize their power , performance and area scaling across imec’s future semiconductor technologies
- Communicate and disseminate research findings through technical presentations, scientific publications, and potential patents.
- Pursuing Masters or PhD in Computer Science/Engineering or equivalent .
- Knowledge of CPU microarchitecture .
- Experience with modelling and simulation tools.
- Some e xperience with RTL .
- Experience with EDA synthesis and simulation s tools is a plus.
- Enthusia s m and curiosity for research and computer architecture
- Strong technical motivation and results driven mindset .
The project will be supervised by researchers at imec in the Compute System Architecture department. imec is a world-renowned research centre for nano-electronics and digital technologies, based in Leuven, Belgium. The student is expected to work from the imec Leuven, Belgium campus full time for a period of 6-9 months, beginning as soon as possible.
References[1] M. Brunion et al ., "CMOS 2.0 - Redefining the Future of Scaling," 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD) , Munich, Germany, 2025, pp. 1-8, doi : 10.1109/ICCAD
[2] S. Li, J. H. Ahn, R.
D. Strong, J.
B. Brockman,
D. M. Tullsen and N. P. Jouppi, " McPAT :
An integrated power, area, and timing modelling framework for multicore and manycore architectures," 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) , New York, NY, USA, 2009, pp. 469-480.
[3] Lakshminarasimhan, Kartik, et al. "The forward slice core microarchitecture." Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques . 2020.
[ 4 ] S. Palacharla , N. P. Jouppi, and J.
E. Smith, “Complexity-Effective Superscalar Processors,” ISCA 1997. [ 5 ]
D. Folegnani and
A. González, “Energy-Effective Issue Logic,” ISCA 2001. [ 6 ] I. Park,
C. L. Ooi, and T. N. Vijaykumar, “Reducing Design Complexity of the Load/Store Queue,” MICRO 2003.
Type of internship
:
PhD internship, Master internship
Duration
: 6 - 9 months
Required educational background
:
Electrotechnics/Electrical Engineering, Computer Science
Supervising scientist(s):
Kartik Lakshminarasimhan (Kart)
The reference code for this position is 2026-INT-336
.
Imec allowance will be provided.
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